Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)

R01UH0042EJ0500 Rev.5.00 Page 381 of 1513

Aug 12, 2011

(d) Conflict between trigger detection and match with CCR0 buffer register

If the trigger is detected immediately after the INTTABnCC0 signal is generated, the 16-bit counter is cleared to

0000H and continues counting up. Therefore, the active period of the TOABnk pin is extended by time from

generation of the INTTABnCC0 signal to trigger detection.

16-bit counter

CCR0 buffer register

INTTABnCC0 signal

TOABnk pin output

External trigger input

(TIAB00 pin input)

Note

D0 − 1D00000FFFF 0000 0000

Extended

Note TAB1: TRGAB1 pin

Remark k = 1 to 3,

n = 0, 1

If the trigger is detected immediately before the INTTABnCC0 signal is generated, the INTTABnCC0 signal is

not generated. The 16-bit counter is cleared to 0000H, the TOABnk pin is asserted, and the counter continues

counting. Consequently, the inactive period of the PWM waveform is shortened.