Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)

R01UH0042EJ0500 Rev.5.00 Page 377 of 1513

Aug 12, 2011

(2) External trigger pulse output mode operation timing

(a) Note on changing pulse width during operation

To change the PWM waveform while the counter is operating, write the TABnCCR1 register last.

Rewrite the TABnCCRk register after writing the TABnCCR1 register after the INTTABnCC0 signal is detected.

FFFFH

16-bit counter

0000H

TABnCE bit

External trigger input

(TIAB00 pin input)

Note

TABnCCR0 register

CCR0 buffer register

INTTABnCC0 signal

TABnCCR1 register

CCR1 buffer register

INTTABnCC1 signal

TOABn1 pin output

TABnCCR2 register

CCR2 buffer register

INTTABnCC2 signal

TOABn2 pin output

TABnCCR3 register

CCR3 buffer register

INTTABnCC3 signal

TOABn3 pin output

TOABn0 pin output

(only when software

trigger is used)

Note TAB1: TRGAB1 pin

Remark n = 0, 1