Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 375 of 1513
Aug 12, 2011
(1) Operation flow in external trigger pulse output mode
Figure 8-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2)
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FFFFH
16-bit counter
0000H
TABnCE bit
External trigger input
(TIAB00 pin input)
Note
TABnCCR0 register
CCR0 buffer register
INTTABnCC0 signal
TOABn0 pin output
(only when software
trigger is used)
TABnCCR1 register
CCR1 buffer register
INTTABnCC1 signal
TOABn1 pin output
TABnCCR2 register
CCR2 buffer register
INTTABnCC2 signal
TOABn2 pin output
TABnCCR3 register
CCR3 buffer register
INTTABnCC3 signal
TOABn3 pin output
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<1> <2> <3> <4> <5> <6> <7>
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Note TAB1: TRGAB1 pin
Remark n = 0, 1