Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 374 of 1513
Aug 12, 2011
Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (3/3)
(d) TABn I/O control register 2 (TABnIOC2)
0 0 0 0 0/1
TABnIOC2
Select valid edge of
external trigger input
0/1 0/1 0/1
TABnETS1 TABnETS0
TABnEES0TABnEES1
Select valid edge of
external event count input
(e) TABn counter read buffer register (TABnCNT)
The value of the 16-bit counter can be read by reading the TABnCNT register.
(f) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
If D
0 is set to the TABnCCR0 register, D1 to the TABnCCR1 register, D2 to the TABnCCR2 register, and D3 to
the TABnCCR3 register, the cycle and active level of the PWM waveform are as follows.
Cycle = (D
0 + 1) × Count clock cycle
TOABn1 pin PWM waveform active level width = D
1 × Count clock cycle
TOABn2 pin PWM waveform active level width = D2 × Count clock cycle
TOABn3 pin PWM waveform active level width = D
3 × Count clock cycle
Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are
not used in the external trigger pulse output mode.
2. Updating TABn capture/compare register 2 (TABnCCR2) and TABn capture/compare
register 3 (TABnCCR3) is enabled by writing TABn capture/compare register 1
(TABnCCR1).
3. n = 0, 1