Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 373 of 1513
Aug 12, 2011
Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (2/3)
(b) TABn control register 1 (TABnCTL1)
0 0/1 0/1 0 0
TABnCTL1
Generate software trigger
when 1 is written
010
TABnMD2 TABnMD1 TABnMD0TABnEST
0, 1, 0:
External trigger pulse
output mode
TABnEEETABnSYE
0: Operate on count clock
selected by TABnCKS0 to
TABnCKS2 bits
1: Count by external event
input signal
(c) TABn I/O control register 0 (TABnIOC0)
0/1 0/1 0/1 0/1 0/1
TABnIOC0
0: Disable TOABn0 pin output
1: Enable TOABn0 pin output
Setting of output level while
operation of TOABn0 pin is disabled
0: Low level
1: High level
0: Disable TOABn1 pin output
1: Enable TOABn1 pin output
Specification of active level
of TOABn1 pin output
0: Active-high
1: Active-low
0/1 0/1
Note
0/1
Note
TABnOE1 TABnOL0 TABnOE0TABnOL1
TOABnk pin output
16-bit counter
• When TABnOLk bit = 0
TOABnk pin output
16-bit counter
• When TABnOLk bit = 1
TABnOE3 TABnOL2 TABnOE2TABnOL3
Specification of active level
of TOABn3 pin output
0: Active-high
1: Active-low
0: Disable TOABn2 pin output
1: Enable TOABn2 pin output
Specification of active level
of TOABn2 pin output
0: Active-high
1: Active-low
0: Disable TOABn3 pin output
1: Enable TOABn3 pin output
Note Clear this bit to 0 when the TOABn0 pin is not used in the external trigger pulse output mode.
Remark n = 0, 1