Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 372 of 1513
Aug 12, 2011
TABn waits for a trigger when the TABnCE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared
from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOABnk pin. If the trigger
is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the
TOABn0 pin is inverted. The TOABnk pin outputs a high level regardless of the status (high/low) when a trigger is
generated.)
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TABnCCRk register) × Count clock cycle
Cycle = (Set value of TABnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TABnCCRk register)/(Set value of TABnCCR0 register + 1)
The compare match request signal (INTTABnCC0) is generated when the 16-bit counter counts up next time after its
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal (INTTABnCCk) is generated when the count value of the 16-bit counter matches the value
of the CCRk buffer register.
The value set to the TABnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H.
The valid edge of the external trigger input signal or setting the software trigger (TABnCTL1.TABnEST bit) to 1 is used
as the trigger.
Remark k = 1 to 3,
m = 0 to 3,
n = 0, 1
Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (1/3)
(a) TABn control register 0 (TABnCTL0)
0/1 0 0 0 0
TABnCTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1 0/1 0/1
TABnCKS2 TABnCKS1 TABnCKS0 TABnCE
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
Remark n = 0, 1