Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 371 of 1513
Aug 12, 2011
Figure 8-17. Basic Timing in External Trigger Pulse Output Mode
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1D1
D2
D3
Active level
width (D
2)
Active level
width (D
2)
Active level
width (D
2)
Active level
width (D
3)
Active level
width (D3)
Cycle (D0 + 1) Cycle (D0 + 1)Wait
for trigger
Active level
width (D
3)
Cycle (D0 + 1)
FFFFH
16-bit counter
0000H
TABnCE bit
External trigger input
(TIAB00 pin input)
Note
TABnCCR0 register
INTTABnCC0 signal
TOABn0 pin output
(only when software
trigger is used)
TABnCCR1 register
INTTABnCC1 signal
TOABn1 pin output
TABnCCR2 register
INTTABnCC2 signal
TOABn2 pin output
TABnCCR3 register
INTTABnCC3 signal
TOABn3 pin output
Active level
width
(D
1)
Active level
width
(D
1)
Active level
width
(D
1)
Active level
width
(D
1)
Active level
width
(D
1)
D
0
D1
D3
D2
D0 D0 D0 D0
Note TAB1: TRGAB1 pin
Remark n = 0, 1