Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 370 of 1513
Aug 12, 2011
8.5.3 External trigger pulse output mode (TABnMD2 to TABnMD0 bits = 010)
In the external trigger pulse output mode, TABn waits for a trigger when the TABnCTL0.TABnCE bit is set to 1. When
the valid edge of the external trigger input signal is detected, TABn starts counting, and outputs a PWM waveform from the
TOABn1 to TOABn3 pins.
Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software
trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOABn0 pin.
Figure 8-16. Configuration in External Trigger Pulse Output Mode
CCR0 buffer register
TABnCE bit
TABnCCR0 register
Clear
Match signal
INTTABnCC0 signal
TOABn3 pin
INTTABnCC3 signal
TOABn0 pin
TIAB00 pin
Note
Transfer
S
R
TABnCCR1
register
CCR1 buffer
register
Match signal
TOABn1 pin
INTTABnCC1 signal
Transfer
Transfer
S
R
TABnCCR3
register
CCR3 buffer
register
Match signal
Transfer
TOABn2 pin
INTTABnCC2 signal
S
R
TABnCCR2
register
CCR2 buffer
register
Match signal
16-bit counter
Count
clock
selection
Count
start
control
Edge
detector
Software trigger
generation
Output
controller
(RS-FF)
Output
controller
Output
controller
(RS-FF)
Output
controller
Note TAB1: TRGAB1 pin
Remark n = 0, 1