Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 368 of 1513
Aug 12, 2011
If the set value of the TABnCCRk register is smaller than the set value of the TABnCCR0 register, the
INTTABnCCk signal is generated once per cycle.
Remark k = 1 to 3,
n = 0, 1
Figure 8-14. Timing Chart When D
01 ≥ Dk1
D 01
D 11
D 21
D 31
D 21
D 11
D 31
D 01 D 01
D 21
D 11
D 31
D 01
D 21
D 11
D 31
D 01
D 21
D 11
D 31
FFFFH
16-bit counter
0000H
TABnCE bit
TABnCCR0 register
INTTABnCC0 signal
TABnCCR1 register
INTTABnCC1 signal
TABnCCR2 register
INTTABnCC2 signal
TABnCCR3 register
INTTABnCC3 signal
Remark n = 0, 1