Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 363 of 1513
Aug 12, 2011
Figure 8-11. Register Setting for Operation in External Event Count Mode (2/2)
(e) TABn counter read buffer register (TABnCNT)
The count value of the 16-bit counter can be read by reading the TABnCNT register.
(f) TABn capture/compare register 0 (TABnCCR0)
If D
0 is set to the TABnCCR0 register, the counter is cleared and a compare match interrupt request
signal (INTTABnCC0) is generated when the number of external event counts reaches (D
0 + 1).
(g) TABn capture/compare registers 1 to 3 (TABnCCR1 to TABnCCR3)
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the external event count mode. However,
the set value of the TABnCCR1 to TABnCCR3 registers are transferred to the CCR1 to CCR3
buffer registers. When the count value of the 16-bit counter matches the value of the CCR1 to
CCR3 buffer registers, compare match interrupt request signals (INTTABnCC1 to INTTABnCC3)
are generated.
Therefore, mask the interrupt signals by using the interrupt mask flags (TABnCCMK1 to TABnCCMK3).
Caution For TAB0, when an external clock is used as the count clock, the external clock can be input
only from the TIAB00 pin. At this time, set the TAB0IOC1.TAB0IS1 and TAB0IOC1.TAB0IS0
bits to 00 (capture trigger input (TIAB00 pin): no edge detection).
Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are
not used in the external event count mode.
2. n = 0, 1