Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 362 of 1513
Aug 12, 2011
When the TABnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts
each time the valid edge of the external event count input is detected. Additionally, the set value of the TABnCCR0 register
is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, and a compare match interrupt request signal (INTTABnCC0) is generated.
The INTTABnCC0 signal is generated each time the valid edge of the external event count input has been detected (set
value of TABnCCR0 register + 1) times.
Figure 8-11. Register Setting for Operation in External Event Count Mode (1/2)
(a) TABn control register 0 (TABnCTL0)
0/1 0 0 0 0
TABnCTL0
0: Stop counting
1: Enable counting
000
TABnCKS2 TABnCKS1 TABnCKS0 TABnCE
(b) TABn control register 1 (TABnCTL1)
00000
TABnCTL1
0, 0, 1:
External event count mode
001
TABnMD2 TABnMD1 TABnMD0TABnEEETABnESTTABnSYE
(c) TABn I/O control register 0 (TABnIOC0)
00000
TABnIOC0
0: Disable TOABn0 pin output
0: Disable TOABn1 pin output
000
TABnOE1 TABnOL0 TABnOE0TABnOL1
TABnOE3 TABnOL2 TABnOE2TABnOL3
0: Disable TOABn2 pin output
0: Disable TOABn3 pin output
(d) TABn I/O control register 2 (TABnIOC2)
0 0 0 0 0/1
TABnIOC2
Select valid edge
of external event
count input
0/1 0 0
TABnEES0 TABnETS1 TABnETS0TABnEES1
Remark n = 0, 1