Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 361 of 1513
Aug 12, 2011
8.5.2 External event count mode (TABnMD2 to TABnMD0 bits = 001)
In the external event count mode, the valid edge of the external event count input is counted when the
TABnCTL0.TABnCE bit is set to 1, and an interrupt request signal (INTTABnCC0) is generated each time the specified
number of edges have been counted. The TOABn0 pin cannot be used.
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the external event count mode.
Figure 8-9. Configuration in External Event Count Mode
16-bit counter
CCR0 buffer registerTABnCE bit
TABnCCR0 register
Edge
detector
Clear
Match signal
INTTABnCC0 signal
TIAB00 pin
Note
(external event
count input)
Note TAB1: EVTAB1 pin
Figure 8-10. Basic Timing in External Event Count Mode
FFFFH
16-bit counter
0000H
TABnCE bit
TABnCCR0 register
INTTABnCC0 signal
D 0
D 0 D 0 D 0
16-bit counter
TABnCCR0 register
INTTABnCC0 signal
External event
count input
(TIAB00 pin input)
Note
D 0
External
event
count
interval
(D
0 + 1)
D 0 − 1D 0 0000 0001
External
event
count
interval
(D
0 + 1)
External
event
count
interval
(D
0 + 1)
Note TAB1: EVTAB1 pin
Remark This figure shows the basic timing when the rising edge is specified as the valid edge of the
external event count input.