Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 357 of 1513
Aug 12, 2011
(c) Notes on rewriting TABnCCR0 register
To change the value of the TABnCCR0 register to a smaller value, stop counting once and then change the set
value.
If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
16-bit counter
0000H
TABnCE bit
TABnCCR0 register
TABnOL0 bit
TOABn0 pin output
INTTABnCC0 signal
D1 D2
D1 D1
D2D2 D2
L
Interval time (1) Interval time (NG) Interval
time (2)
Remarks 1. Interval time (1): (D
1 + 1) × Count clock cycle
Interval time (NG): (10000H + D
2 + 1) × Count clock cycle
Interval time (2): (D
2 + 1) × Count clock cycle
2. n = 0, 1
If the value of the TABnCCR0 register is changed from D
1 to D2 while the count value is greater than D2 but
less than D
1, the count value is transferred to the CCR0 buffer register as soon as the TABnCCR0 register has
been rewritten. Consequently, the value of the 16-bit counter that is compared is D2.
Because the count value has already exceeded D
2, however, the 16-bit counter counts up to FFFFH, overflows,
and then counts up again from 0000H. When the count value matches D
2, the INTTABnCC0 signal is
generated and the output of the TOABn0 pin is inverted.
Therefore, the INTTABnCC0 signal may not be generated at the interval time “(D
1 + 1) × Count clock cycle” or
“(D
2 + 1) × Count clock cycle” originally expected, but may be generated at an interval of “(10000H + D2 + 1) ×
Count clock period”.