Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 356 of 1513
Aug 12, 2011
(2) Interval timer mode operation timing
(a) Operation if TABnCCR0 register is set to 0000H
If the TABnCCR0 register is set to 0000H, the INTTABnCC0 signal is generated at each count clock
subsequent to the first count clock, and the output of the TOABn0 pin is inverted.
The value of the 16-bit counter is always 0000H.
Count clock
16-bit counter
TABnCE bit
TABnCCR0 register
TOABn0 pin output
INTTABnCC0 signal
0000H
Interval time
Count clock cycle
Interval time
Count clock cycle
FFFFH 0000H 0000H 0000H 0000H
Remark n = 0, 1
(b) Operation if TABnCCR0 register is set to FFFFH
If the TABnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to
0000H in synchronization with the next count-up timing. The INTTABnCC0 signal is generated and the output
of the TOABn0 pin is inverted. At this time, an overflow interrupt request signal (INTTABnOV) is not generated,
nor is the overflow flag (TABnOPT0.TABnOVF bit) set to 1.
FFFFH
16-bit counter
0000H
TABnCE bit
TABnCCR0 register
TOABn0 pin output
INTTABnCC0 signal
FFFFH
Interval time
10000H ×
count clock cycle
Interval time
10000H ×
count clock cycle
Interval time
10000H ×
count clock cycle
Remark n = 0, 1