Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 355 of 1513
Aug 12, 2011
(1) Interval timer mode operation flow
Figure 8-5. Software Processing Flow in Interval Timer Mode
FFFFH
16-bit counter
0000H
TABnCE bit
TABnCCR0 register
TOABn0 pin output
INTTABnCC0 signal
D 0
D 0 D 0 D 0
<1> <2>
TABnCE bit = 1
TABnCE bit = 0
Register initial setting
TABnCTL0 register
(TABnCKS0 to TABnCKS2 bits)
TABnCTL1 register,
TABnIOC0 register,
TABnCCR0 register
The initial setting of these registers is performed
before setting the TABnCE bit to 1.
The TABnCKS0 to TABnCKS2 bits can be
set at the same time when counting has
been started (TABnCE bit = 1).
The counter is initialized and counting is
stopped by clearing the TABnCE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
Remark n = 0, 1