Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 354 of 1513
Aug 12, 2011
Figure 8-4. Register Setting for Interval Timer Mode Operation (2/2)
(c) TABn I/O control register 0 (TABnIOC0)
0/1 0/1 0/1 0/1 0/1
TABnIOC0
0: Disable TOABn0 pin output
1: Enable TOABn0 pin output
Setting of output level with
operation of TOABn0 pin disabled
0: Low level
1: High level
0: Disable TOABn1 pin output
1: Enable TOABn1 pin output
Setting of output level with
operation of TOABn1 pin disabled
0: Low level
1: High level
0/1 0/1 0/1
TABnOE1 TABnOL0 TABnOE0TABnOL1
0: Disable TOABn2 pin output
1: Enable TOABn2 pin output
Setting of output level with
operation of TOABn2 pin disabled
0: Low level
1: High level
0: Disable TOABn3 pin output
1: Enable TOABn3 pin output
Setting of output level with
operation of TOABn3 pin disabled
0: Low level
1: High level
TABnOE3 TABnOL2 TABnOE2TABnOL3
(d) TABn counter read buffer register (TABnCNT)
By reading the TABnCNT register, the count value of the 16-bit counter can be read.
(e) TABn capture/compare register 0 (TABnCCR0)
If the TABnCCR0 register is set to D
0, the interval is as follows.
Interval = (D
0 + 1) × Count clock cycle
(f) TABn capture/compare registers 1 to 3 (TABnCCR1 to TABnCCR3)
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the interval timer mode. However, the set
value of the TABnCCR1 to TABnCCR3 registers is transferred to the CCR1 to CCR3 buffer
registers. The compare match interrupt request signals (INTTABnCCR1 to INTTABnCCR3) are
generated when the count value of the 16-bit counter matches the value of the CCR1 to CCR3
buffer registers.
Therefore, mask the interrupt requests by using the corresponding interrupt mask flags (TABnCCMK1 to
TABnCCMK3).
Remarks 1. TABn I/O control register 1 (TABnIOC1), TABn I/O control register 2 (TABnIOC2), and
TABn option register 0 (TABnOPT0) are not used in the interval timer mode.
2. n = 0, 1