Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 353 of 1513
Aug 12, 2011
When the TABnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
with the count clock, and the counter starts counting. At this time, the output of the TOABn0 pin is inverted. Additionally,
the set value of the TABnCCR0 register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, the output of the TOABn0 pin is inverted, and a compare match interrupt request signal (INTTABnCC0) is
generated.
The interval can be calculated by the following expression.
Interval = (Set value of TABnCCR0 register + 1) × Count clock cycle
Figure 8-4. Register Setting for Interval Timer Mode Operation (1/2)
(a) TABn control register 0 (TABnCTL0)
0/1 0 0 0 0
C
TL0
Select count clock
0: Stop counting
1: Enable counting
0/1 0/1 0/1
TABnCKS2 TABnCKS1 TABnCKS0 TABnCE
(b) TABn control register 1 (TABnCTL1)
0 0 0/1
Note
00
C
TL1
0, 0, 0:
Interval timer mode
000
TABnMD2 TABnMD1 TABnMD0TABnEEETABnESTTABnSYE
0: Operate on count
clock selected by bits
TABnCKS0 to TABnCKS2
1: Count with external
event count input signal
Note This bit can be set to 1 only when the interrupt request signals (INTTABnCC0 and INTTABnCCk) are
masked by the interrupt mask flags (TABnCCMK0 to TABnCCMKk) and the timer output (TOABnk) is
performed at the same time. However, the TABnCCR0 and TABnCCRk registers must be set to the
same value (see 8.5.1 (2) (d) Operation of TABnCCR1 to TABnCCR3 registers) (k = 1 to 3).
Remark n = 0, 1