Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 352 of 1513
Aug 12, 2011
8.5.1 Interval timer mode (TABnMD2 to TABnMD0 bits = 000)
In the interval timer mode, an interrupt request signal (INTTABnCC0) is generated at the specified interval if the
TABnCTL0.TABnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOABn0
pin.
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the interval timer mode.
Figure 8-2. Configuration of Interval Timer
16-bit counter
Output
controller
CCR0 buffer registerTABnCE bit
TABnCCR0 register
Count clock
selection
Clear
Match signal
TOABn0 pin
INTTABnCC0 signal
Remark n = 0, 1
Figure 8-3. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
0000H
TABnCE bit
TABnCCR0 register
TOABn0 pin output
INTTABnCC0 signal
D 0
D 0 D 0 D 0 D 0
Interval (D 0 + 1) Interval (D 0 + 1) Interval (D 0 + 1) Interval (D 0 + 1)
Remark n = 0, 1