Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 350 of 1513
Aug 12, 2011
(12) TABn counter read buffer register (TABnCNT)
The TABnCNT register is a read buffer register that can read the count value of the 16-bit counter.
If this register is read when the TABnCTL0.TABnCE bit = 1, the count value of the 16-bit timer can be read.
This register is read-only in 16-bit units.
The value of the TABnCNT register is cleared to 0000H when the TABnCE bit = 0. If the TABnCNT register is read
at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read.
The value of the TABnCNT register is cleared to 0000H after reset, as the TABnCE bit is cleared to 0.
Caution Accessing the TABnCNT register is prohibited in the following statuses. For details, see 3.4.9 (2)
Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
TABnCCR0
(n = 0, 1)
12 10 8 6 4 2
After reset: 0000H R/W Address: TAB0CCR0 FFFFF546H, TAB1CCR0 FFFFF566H
14 0
13 11 9 7 5 3
15 1