Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 341 of 1513
Aug 12, 2011
(7) TABn option register 0 (TABnOPT0)
The TABnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TABnCCS3
TABnCCSm
0
1
TABnCCRm register capture/compare selection
The TABnCCSm bit setting is valid only in the free-running timer mode.
Compare register selected
Capture register selected
TABnOPT0
(n = 0, 1)
TABnCCS2 TABnCCS1 TABnCCS0 0 TAB1CMS
Note
TABnCUF TABnOVF
654321
After reset: 00H R/W Address: TAB0OPT0 FFFFF545H, TAB1OPT0 FFFFF565H
TABnOVF
Set (1)
Reset (0)
TABn overflow detection
• The TABnOVF bit is set to 1 when the 16-bit counter count value overflows from
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
• An interrupt request signal (INTTABnOV) is generated at the same time that the
TABnOVF bit is set to 1. The INTTABnOV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
• The TABnOVF bit is not cleared even when the TABnOVF bit or the TABnOPT0
register are read when the TABnOVF bit = 1.
• The TABnOVF bit can be both read and written, but the TABnOVF bit cannot be
set to 1 by software. Writing 1 has no effect on the operation of TABn.
Overflow occurred
TABnOVF bit 0 written or TABnCTL0.TABnCE bit = 0
7 0
Note The TAB1CMS bit is used for the motor control function. For details,
see CHAPTER 11 MOTOR CONTROL FUNCTION.
Cautions 1. Rewrite the TABnCCS3 to TABnCCS0 bits when the
TABnCTL0.TABnCE bit = 0. (The same value can be
written when the TABnCE bit = 1.) If rewriting was
mistakenly performed, clear the TABnCE bit to 0 and then
set the bits again.
2. Be sure to set bit 3 to “0”. When the motor control
function is not used, be sure to also set bit 2 to “0”.
Remark m = 0 to 3