Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 339 of 1513
Aug 12, 2011
(5) TABn I/O control register 2 (TABnIOC2)
The TABnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal
(TIAB00/EVTAB1 pin) and external trigger input signal (TIAB00/TRGAB1 pin).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
TABnEES1
0
0
1
1
TABnEES0
0
1
0
1
External event count input signal (TIAB00/EVTAB1 pin) valid edge setting
No edge detection (external event count invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
TABnIOC2
(n = 0, 1)
000
TABnEES1 TABnEES0 TABnETS1 TABnETS0
654321
After reset: 00H R/W Address: TAB0IOC2 FFFFF544H, TAB1IOC2 FFFFF564H
TABnETS1
0
0
1
1
TABnETS0
0
1
0
1
External trigger input signal (TIAB00/TRGAB1 pin) valid edge setting
No edge detection (external trigger invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
7 0
Cautions 1. Rewrite the TABnEES1, TABnEES0, TABnETS1, and
TABnETS0 bits when the TABnCTL0.TABnCE bit = 0. (The
same value can be written when the TABnCE bit = 1.) If
rewriting was mistakenly performed, clear the TABnCE bit
to 0 and then set the bits again.
2. The TABnEES1 and TABnEES0 bits are valid only when the
TABnCTL1.TABnEEE bit = 1 or when the external event
count mode (TABnCTL1.TABnMD2 to TABnCTL1.TABnMD0
bits = 001) has been set.
3. The TABnETS1 and TABnETS0 bits are valid only when the
external trigger pulse output mode (TABnCTL1.TABnMD2
to TABnCTL1.TABnMD0 bits = 010) or the one-shot pulse
output mode (TABnCTL1.TABnMD2 to
TABnCTL1.TABnMD0 = 011) is set.