Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 338 of 1513
Aug 12, 2011
(4) TABn I/O control register 1 (TABnIOC1)
The TABnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIABn0
to TIABn3 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TABnIS7
TABnIS7
0
0
1
1
TABnIS6
0
1
0
1
Capture trigger input signal (TIABn3 pin) valid edge setting
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
TABnIOC1
(n = 0, 1)
TABnIS6 TABnIS5 TABnIS4 TABnIS3 TABnIS2 TABnIS1 TABnIS0
654321
After reset: 00H R/W Address: TAB0IOC1 FFFFF543H, TAB1IOC1 FFFFF563H
TABnIS5
0
0
1
1
TABnIS4
0
1
0
1
Capture trigger input signal (TIABn2 pin) valid edge detection
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
7 0
TABnIS3
0
0
1
1
TABnIS2
0
1
0
1
Capture trigger input signal (TIABn1 pin) valid edge setting
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
TABnIS1
0
0
1
1
TABnIS0
0
1
0
1
Capture trigger input signal (TIABn0 pin) valid edge setting
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
Cautions 1. Rewrite the TABnIS7 to TABnIS0 bits when the
TABnCTL0.TABnCE bit = 0. (The same value can be
written when the TABnCE bit = 1.) If rewriting was
mistakenly performed, clear the TABnCE bit to 0 and then
set the bits again.
2. The TABnIS7 to TABnIS0 bits are valid only in the free-
running timer mode and the pulse width measurement
mode. In all other modes, a capture operation is not
possible.