Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 334 of 1513
Aug 12, 2011
8.4 Registers
The registers that control TABn are as follows.
• TABn control register 0 (TABnCTL0)
• TABn control register 1 (TABnCTL1)
• TABn I/O control register 0 (TABnIOC0)
• TABn I/O control register 1 (TABnIOC1)
• TABn I/O control register 2 (TABnIOC2)
• TABn I/O control register 4 (TABnIOC4)
• TABn option register 0 (TABnOPT0)
• TABn capture/compare register 0 (TABnCCR0)
• TABn capture/compare register 1 (TABnCCR1)
• TABn capture/compare register 2 (TABnCCR2)
• TABn capture/compare register 3 (TABnCCR3)
• TABn counter read buffer register (TABnCNT)
Remarks 1. When using the functions of the TIABn0 to TIABn3 and TOABn0 to TOABn3 pins, see Table 4-20 Using
Port Pin as Alternate-Function Pin.
2. n = 0, 1