Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 331 of 1513
Aug 12, 2011
8.3 Configuration
TABn includes the following hardware.
Table 8-1. Configuration of TABn
Item Configuration
Registers
16-bit counter
TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
TABn counter read buffer register (TABnCNT)
CCR0 to CCR3 buffer registers
TABn control registers 0, 1 (TABnCTL0, TABnCTL1)
TABn I/O control registers 0 to 2 (TABnIOC0 to TABnIOC2, TABnIOC4)
TABn option register 0 (TABnOPT0)
Timer inputs
Note 2
4 (TIABn0
Note 1
to TIABn3 pins)
Timer outputs
Note 2
4 (TOABn0 to TOABn3 pins)
Notes 1. When using the functions of the TIABn0 to TIABn3 and TOABn0 to TOABn3 pins, see Table 4-20
Using Port Pin as Alternate-Function Pin.
2. The TIAB00 pin functions alternately as a capture trigger input signal, external event count input
signal, and external trigger input signal.
Figure 8-1. Block Diagram of TABn
TABnCNT
TABnCCR0
TABnCCR1
TABnCCR2
TOABn0
INTTABnOV
CCR2
buffer
register
TABnCCR3
CCR3
buffer
register
TOABn1
TOABn2
TOABn3
INTTABnCC0
INTTABnCC1
INTTABnCC2
INTTABnCC3
fXX
fXX/2
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
fXX/128
TIABn0
Note
TIABn1
TIABn2
TIABn3
Selector
Internal bus
Internal bus
Selector
Edge detector
CCR0
buffer
register
CCR1
buffer
register
16-bit counter
Output
controller
Clear
Note TAB1: EVTAB1 pin and TRGAB1 pin
Remarks 1. f
XX: Main clock frequency
2. n = 0, 1