Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 327 of 1513
Aug 12, 2011
Figure 7-52. Example of Basic Timing When TAA1 and TAA0 Are Connected in Cascade
32-bit counter
FFFFFFFFH
00000000H
Operation enable bit
(
TAA1CE)
TIAA10 input
D
0a0b
D0c0d
D1c1d
D0e0f
D1e1f
D 1g1h
D0g0h
D0i0j
Lower capture register 0
(TAA1CCR0)
Lower capture interrupt 0
(INTTAA1CC0)
TIAA11 input
Capture interrupt 1
(INTTAA1CC1)
Overflow interrupt
(INTTAA0OV)
Overflow flag
(TAA0OVF)
Pulse interval
D 1c1d − D 1a1b
Pulse interval
D 1g1h − D 1c1d
Pulse interval
D 1e1f − D 1c1d
D1a1b
Pulse interval
D0c0d − D0a0b
Pulse interval
D0e0f − D0c0d
Pulse interval
D 0g0h − D 0c0d
Pulse interval
D 0i0j − D 0g0h
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
D0b D0d D 0f D 0h D 0j
0000
Higher capture register 0
(TAA0CCR0)
Lower capture register 1
(TAA1CCR1)
Higher capture register 1
(TAA0CCR1)
D0a D0c D 0e D 0g D 0i
0000
D
1d D 1f D 1h D1b0000
D1c D 1e D 1g D1a0000
The counting operation is started when the TAA1CTL.TAA1CE bit is set to 1 and the count clock is supplied.
When the valid edge input to the TIAA10 pin is detected, the count value is stored in the capture register 0
(TAA1CCR0 and TAA0CCR0), and capture interrupt 0 signal (INTTAA1CC0) is issued.
The timer counter continues the counting operation in synchronization with the count clock. When it counts
up to FFFFFFFFH, the overflow interrupt (INTTAA0OV) is generated at the next clock and the overflow flag
(TAA0OVF) is set to 1. The timer counter is cleared to 00000000H and continues counting up.
The overflow flag (TAA0OVF) is cleared by an instruction issued from the CPU that writes “0” to it.
Because the free-running timer mode is set, the timer counter cannot be cleared by detection of the valid
edge input to the TIAA10 pin.
Using TOAA10 output is prohibited because it alternately functions as the TIAA10 input.
Capture register 1 (TAA1CCR1 and TAA0CCR1) also operates in the same manner.
If the lower timer counter (TAA1) overflows, an overflow interrupt (TAA1OVF) is generated. However, it is
recommended to mask this interrupt because it cannot be used as an overflow interrupt of the 32-bit counter.