Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 326 of 1513
Aug 12, 2011
Figure 7-51. Operation Flow in Cascade Connection of TAA1 and TAA0 (2/2)
TAA1CE bit = 1
Reading TAA0OPT0 register
(checking overflow flag)
[Lower timer: TAA1]
TAA1CTL0 register
(TAA1CKS0 to TAA1CKS2 bits),
TAA1CTL1 register,
TAA1IOC1 register,
TAA1IOC2 register,
TAA1OPT0 register
[Higher timer: TAA0]
TAA0CTL1 register,
TAA0IOC1 register,
TAA0OPT0 register,
TAA0OPT1 register
Perform initial setting
of these registers
before TAA1CE bit = 1.
TAA1CKS0 to TAA1CKS2 bits
can be set as soon as counting
operation starts
(TAA1CE bit = 1).
START
Executing instruction that clears
TAA0OVF bit (CLR TAA0OVF)
<1> Count operation start flow
<4> Overflow flag clear flow
TAA1CE bit = 0
Counter is initialized by
stopping counting operation
(TAA1CE bit = 0).
STOP
<5> Count operation stop flow
TAA0OVF bit = 1
NO
YES
Reading TAA1CCR0 and
TAA0CCR0 registers
(reading capture register 0)
Executing instruction that clears
TAA0CCIC0.TAA0CCIF0 bit
(
CLR TAA0CCIF0)
Calculating pulse interval
(Captured value − Previously
captured value)
<2> Capture 0 read flow
INTTAA0CCR0 generated?
NO
YES
TAA1CCIF0 = 0?
NO
YES
Reading TAA1CCR1 and
TAA0CCR1 registers
(reading capture register 0)
Executing instruction that clears
TAA0CCIC1.TAA0CCIF1 bit
(
CLR TAA0CCIF1)
Calculating pulse interval
(Captured value − Previously
captured value)
INTTAA0CCR1 generated?
NO
YES
TAA0CCIF1 = 0?
NO
YES
<2> Capture 1 read flow
Register initial setting