Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 325 of 1513
Aug 12, 2011
Figure 7-51. Operation Flow in Cascade Connection of TAA1 and TAA0 (1/2)
32-bit counter
FFFFFFFFH
00000000H
Operation enable bit
(
TAA1CE)
TIAA10 input
D
0a0b
D0c0d
D1c1d
D0e0f
D1e1f
D0g0h
Lower capture register 0
(TAA1CCR0)
Lower capture interrupt 0
(INTTAA1CC0)
TIAA11 input
Lower capture interrupt 1
(INTTAA1CC1)
Overflow interrupt
(INTTAA0OV)
Overflow flag
(TAA0OVF)
Pulse interval
D 1c1d − D 1a1b
Pulse interval
D 1e1f − D 1c1d
D1a1b
Pulse interval
D0c0d − D0a0b
Pulse interval
D0e0f − D0c0d
Pulse interval
D 0g0h − D 0c0d
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
D0b D0d D 0f D 0h
0000
Higher capture register 0
(TAA0CCR0)
Lower capture register 1
(TAA1CCR1)
Higher capture register 1
(TAA0CCR1)
D0a D0c D 0e D 0g
0000
D
1d D 1f D1b0000
D1c D 1e 0000H
0000H
0000H
0000H
D1a0000
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