Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 323 of 1513
Aug 12, 2011
7.8 Cascade Connection
This section explains an operation of connecting two channels of TAA in cascade to form a 32-bit capture timer.
For cascade connection, the free-running timer mode must be set and all the capture/compare registers must be set as
capture registers (TAA0CCSn = 1).
Combinations of TAA channels that can be connected in cascade are shown in the following table.
Table 7-11. Cascade Connection of TAA
Lower Timer (Master Timer) Higher Timer (Slave Timer)
TAA1 TAA0
TAA3 TAA2
In the following example, TAA1 is used as the lower timer (master timer) and TAA0 is used as the higher timer (slave
timer) to use them as a 32-bit capture timer by cascade connection.
Figure 7-50. Cascade Connection Example
Edge
detection
Count
clock
selection
Operation enable
bit (TAA1CE)
FFFFH
detection
signal
Capture signal 1
(TIAA11)
Capture signal 0
(TIAA10)
Lower capture interrupt 0
(INTTAA1CC0)
Lower overflow interrupt
(INTTAA1OV)
Lower capture interrupt 1
(INTTAA1CC1)
[Lower timer TAA1] [Higher timer TAA0]
Lower timer counter
Lower capture register 0
(TAA1CCR0)
Lower capture register 1
(TAA1CCR1)
Higher timer counter
Higher capture register 0
(TAA0CCR0)
Higher capture register 1
(TAA0CCR1)
Higher overflow interrupt
(INTTAA0OV)
Edge
detection