Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 318 of 1513
Aug 12, 2011
7.6.2 PWM output mode (during timer-tuned operation)
This section explains the PWM output mode of timer-tuned operation. For combinations of timer-tuned operations, see
Table 7-7. This section presents an example of a timer-tuned operation with TAB0 and TAA5.
The TAB0CCR0 register of the master timer (TAB0) is used as a compare register for cycle, and the TAB0CCR1,
TAB0CCR2, and TAB0CCR3 registers of the master timer (TAB0) and the TAA5CCR0 and TAA5CCR1 registers of the
slave timer (TAA5) are used as compare registers for duty.
The compare registers can be rewritten during operation and the rewriting method is batch writing.
Batch writing is enabled when the TAB0CCR1 register of the master timer (TAB0) is written, and all the compare
registers of the master and slave timers are rewritten or the same value is written to them when an interrupt, which is
generated if the value of the TAB0CCR0 register of the master timer (TAB0) matches the value of the timer counter, is
generated.
(1) Settings in PWM output mode
[Initials setting]
Master timer: TAB0CTL0.TAB0CE = 0 (operation disabled)
Slave timer: TAA5CTL0.TAA5CE = 0 (operation disabled)
[Initial settings of master timer (TAB0)]
• TAB0CTL1.TAB0MD2 to TAB0CTL1.TAB0MD0 = 100 (setting of PWM output mode)
• TAB0OPT0.TAB0CCS3 to TAB0OPT0.TAB0CCS0 = 0000 (setting of capture/compare select bit to
“compare”.)
• TAB0CCR0, TAB0CCR1, TAB0CCR2, and TAB0CCR3 registers are set.
[Initial settings of slave timer (TAA5)]
• TAA5CTL1.TAA5SYE = 1 (setting of timer-tuned operation)
• TAA5CTL1.TAA5MD2 to TAA5CTL1.TAA5MD0 = 101 (setting of free-running timer mode)
• TAA5OPT0.TAA5CCS1 and TAA5OPT0.TAA5CCS0 = 00 (setting of capture/compare select bit to
“compare”.)
• TAA5CCR0 and TAA5CCR1 registers are set.
Remark The initial settings of the master timer and slave timer may be performed in any order.
[Starting counting]
<1> Set TAB0CTL0.TAB0CE of the master timer to 1.
<2> Start counting.
<3> Changing the setting of the register during operation
• The compare register can be rewritten (batch rewrite).
[End condition]
• Set TAB0CTL0.TAB0CE of the master timer to 0.