Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 1 INTRODUCTION
R01UH0042EJ0500 Rev.5.00 Page 31 of 1513
Aug 12, 2011
(9) Real-time counter (for watch)
The real-time counter counts the reference time (one second) for watch counting based on the subclock (32.768
kHz) or main clock. This can simultaneously be used as the interval timer based on the main clock. Hardware
counters dedicated to year, month, day of week, day, hour, minute, and second are provided, and can count up to
99 years.
(10) Watchdog timer 2
A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc.
The internal oscillation clock, the main clock, or the subclock can be selected as the source clock.
Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal
(WDT2RES) after an overflow occurs.
(11) Serial interface
The V850ES/JG3-H and V850ES/JH3-H include three kinds of serial interfaces (asynchronous serial interface C
(UARTC), 3-wire variable-length serial interface F (CSIF), and an I
2
C bus interface (I
2
C)), a CAN controller
(CAN)
Note
, and a USB function controller (USBF).
UARTC transfers data via the TXDC0 to TXDC2 pins and RXDC0 to RXDC2 pins.
CSIF transfers data via the SOF0 to SOF4 pins, SIF0 to SIF4 pins, and SCKF0 to SCKF4 pins.
In the case of I
2
C, data is transferred via the SDA00 to SDA02 and SCL00 to SCL02 pins.
CAN
Note
transfers data via the CRXD0
Note
and CTXD0
Note
pins.
USBF transfers data via the UDMF and UDPF pins.
Note
μ PD70F3770, 70F3771 only
(12) A/D converter
This 10-bit A/D converter includes 12 analog input pins. Conversion is performed using the successive
approximation method.
(13) D/A converter
A two-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip.
(14) DMA controller
A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM, on-chip
peripheral I/O devices, and external memory in response to interrupt requests sent by on-chip peripheral I/O
devices.
(15) Key interrupt function
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8
channels).
(16) Real-time output function
The real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer compare
register match signal.
(17) CRC function
A CRC operation circuit that generates a 16-bit CRC (Cyclic Redundancy Check) code upon setting of 8-bit data
is provided on-chip.