Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 305 of 1513
Aug 12, 2011
Figure 7-41. Register Setting in Pulse Width Measurement Mode
(a) TAAn control register 0 (TAAnCTL0)
0/1 0 0 0 0
TAAnCTL0
Select count clock
0: Stops counting
1: Enables counting
0/1 0/1 0/1
TAAnCKS2 TAAnCKS1 TAAnCKS0 TAAnCE
(b) TAAn control register 1 (TAAnCTL1)
00000
TAAnCTL1
110
TAAnMD2TAAnEST TAAnEEE TAAnMD1 TAAnMD0
1, 1, 0:
Pulse width measurement
mode
(c) TAAn I/O control register 1 (TAAnIOC1)
0 0 0 0 0/1
TAAnIOC1
Select valid edge
of TIAAn0 pin input
Select valid edge
of TIAAn1 pin input
0/1 0/1 0/1
TAAnIS2 TAAnIS1 TAAnIS0TAAnIS3
(d) TAAn option register 0 (TAAnOPT0)
00000
TAAnOPT0
Overflow flag
0 0 0/1
TAAnOVF
TAAnCCS1 TAAnCCS0
(e) TAAn counter read buffer register (TAAnCNT)
The value of the 16-bit counter can be read by reading the TAAnCNT register.
(f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1)
These registers store the count value of the 16-bit counter when the valid edge input to the TIAAnm pin is
detected.
Remarks 1. TAAn I/O control register 0 (TAAnIOC0), and TAAn I/O control register 2 (TAAnIOC2) are not
used in the pulse width measurement mode.
2. m = 0, 1
n = 0 to 3, 5