Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 304 of 1513
Aug 12, 2011
Figure 7-40. Basic Timing in Pulse Width Measurement Mode
FFFFH
16-bit counter
0000H
TAAnCE bit
TIAAnm pin input
TAAnCCRm register
INTTAAnCCm signal
INTTAAnOV signal
TAAnOVF bit
D 0 0000H D 1 D 2 D 3
Cleared to 0 by
CLR instruction
Remark n = 0 to 3, 5
m = 0, 1
When the TAAnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIAAnm pin is
later detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, the 16-bit counter is cleared to
0000H, and a capture interrupt request signal (INTTAAnCCm) is generated.
The pulse width is calculated as follows.
Pulse width = Captured value × Count clock cycle
If the valid edge is not input to the TIAAnm pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt
request signal (INTTAAnOV) is generated at the next count clock, and the counter is cleared to 0000H and continues
counting. At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by
executing the CLR instruction via software.
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Pulse width = (10000H × TAAnOVF bit set (1) count + Captured value) × Count clock cycle
Remark n = 0 to 3, 5
m = 0, 1