Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 1 INTRODUCTION
R01UH0042EJ0500 Rev.5.00 Page 30 of 1513
Aug 12, 2011
1.6.2 Internal units
(1) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic
operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits)
contribute to faster complex processing.
(2) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU
generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an
instruction queue.
(3) Flash memory (ROM)
This is a 512/384/256 KB flash memory mapped to addresses 0000000H to 007FFFFH/0000000H to
005FFFFH/0000000H to 003FFFFH. It can be accessed from the CPU in one clock during instruction fetch.
(4) RAM
This is a 48/40/32 KB RAM mapped to addresses 3FF3000H to 3FFEFFFH/3FF5000H to 3FFEFFFH/3FF7000H to
3FFEFFFH. It can be accessed from the CPU in one clock during data access. An 8 KB data-only RAM is
incorporated at addresses 00280000H to 002FFFFFH.
(5) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP18) from on-chip peripheral hardware and
external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed
servicing control can be performed.
(6) Clock generator (CG)
A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (f
X)
and subclock frequency (f
XT), respectively. There are two modes: In the clock-through mode, fX is used as the main
clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 8.
The CPU clock frequency (f
CPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT.
(7) Internal oscillator
An internal oscillator is provided on chip. The oscillation frequency is 220 kHz (TYP). The internal oscillator
supplies the clock for watchdog timer 2 and timer M.
(8) Timer/counter
Six-channel 16-bit timer/event counter AA (TAA), two-channel 16-bit timer/event counter AB (TAB), one-channel 16-
bit timer/event counter T (TMT), and four-channel 16-bit interval timer M (TMM) are provided on chip. The motor
control function can be realized using TAB1 and TAA4 in combination.