Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 297 of 1513
Aug 12, 2011
(c) Processing of overflow when two capture registers are used
Care must be exercised in processing the overflow flag when two capture registers are used. First, an example
of incorrect processing is shown below.
Example of incorrect processing when two capture registers are used
FFFFH
16-bit counter
0000H
TAAnCE bit
TIAAn0 pin input
TAAnCCR0 register
TIAAn1 pin input
TAAnCCR1 register
INTTAAnOV signal
TAAnOVF bit
D
00
D
01
D
10
D
11
D
10
<1> <2> <3> <4>
D
00
D
11
D
01
The following problem may occur when two pulse widths are measured in the free-running timer mode.
<1> Read the TAAnCCR0 register (setting of the default value of the TIAAn0 pin input).
<2> Read the TAAnCCR1 register (setting of the default value of the TIAAn1 pin input).
<3> Read the TAAnCCR0 register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
01 − D00).
<4> Read the TAAnCCR1 register.
Read the overflow flag. Because the flag is cleared in <3>, 0 is read.
Because the overflow flag is 0, the pulse width can be calculated by (D
11 − D10) (incorrect).
When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other
capture register may not obtain the correct pulse width.
Use software when using two capture registers. An example of how to use software is shown below.