Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 295 of 1513
Aug 12, 2011
(2) Operation timing in free-running timer mode
(a) Interval operation with TAAnCCRm register used as compare register
When 16-bit timer/event counter AA is used as an interval timer with the TAAnCCRm register used as a
compare register, software processing is necessary for setting a comparison value to generate the next
interrupt request signal each time the INTTAAnCCm signal has been detected.
FFFFH
16-bit counter
0000H
TAAnCE bit
TAAnCCR0 register
INTTAAnCC0 signal
TOAAn0 pin output
TAAnCCR1 register
INTTAAnCC1 signal
TOAAn1 pin output
D 00 D 01 D 02 D 03 D 04 D 05
D 10
D 00
D 11
D 01
D 12
D 04
D 13
D 02
D 03
D 11 D 10 D 12 D 13 D 14
Interval period
(D
10 + 1)
Interval period
(10000H
+
D11 − D10)
Interval period
(10000H
+
D12 − D11)
Interval period
(10000H
+
D13 − D12)
Interval period
(D
00 + 1)
Interval period
(10000H +
D
01 − D 00 )
Interval period
(D
02 − D 01 )
Interval period
(10000H +
D
03 − D 02 )
Interval period
(10000H +
D
04 − D 03 )
When performing an interval operation in the free-running timer mode, two intervals can be set with one
channel.
To perform the interval operation, the value of the corresponding TAAnCCRm register must be re-set in the
interrupt servicing that is executed when the INTTAAnCCm signal is detected.
The set value for re-setting the TAAnCCRm register can be calculated by the following expression, where “D
m”
is the interval period.
Compare register default value: D
m − 1
Value set to compare register second and subsequent times: Previous set value + Dm
(If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the
register.)
Remark m = 0, 1
n = 0 to 3, 5