Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)

R01UH0042EJ0500 Rev.5.00 Page 292 of 1513

Aug 12, 2011

Figure 7-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2)

TAAnCE bit = 1

Read TAAnOPT0 register

(check overflow flag).

TAAnCTL0 register

(TAAnCKS0 to TAAnCKS2 bits),

TAAnCTL1 register,

TAAnIOC0 register,

TAAnIOC2 register,

TAAnOPT0 register,

TAAnCCR0 register,

TAAnCCR1 register

Initial setting of these registers

is performed before setting the

TAAnCE bit to 1.

The TAAnCKS0 to TAAnCKS2 bits

can be set at the same time

when counting has been started

(TAAnCE bit = 1).

START

Execute instruction to clear

TAAnOVF bit (CLR TAAnOVF).

<1> Count operation start flow

<2> Overflow flag clear flow

TAAnCE bit = 0

Counter is initialized and

counting is stopped by

clearing TAAnCE bit to 0.

STOP

<3> Count operation stop flow

TAAnOVF bit = 1

YES

Remark n = 0 to 3, 5