Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 290 of 1513
Aug 12, 2011
Figure 7-36. Register Setting in Free-Running Timer Mode (2/2)
(d) TAAn I/O control register 1 (TAAnIOC1)
0 0 0 0 0/1
TAAnIOC1
Select valid edge
of TIAAn0 pin input
Select valid edge
of TIAAn1 pin input
0/1 0/1 0/1
TAAnIS2 TAAnIS1 TAAnIS0TAAnIS3
(e) TAAn I/O control register 2 (TAAnIOC2)
0 0 0 0 0/1
TAAnIOC2
Select valid edge of
external event count input
0/1 0 0
TAAnEES0 TAAnETS1 TAAnETS0TAAnEES1
(f) TAAn option register 0 (TAAnOPT0)
0 0 0/1 0/1 0
TAAnOPT0
Overflow flag
Specifies if TAAnCCR0
register functions as
capture or compare register
Specifies if TAAnCCR1
register functions as
capture or compare register
0 0 0/1
TAAnCCS0 TAAnOVF TAAnCCS1
(g) TAAn counter read buffer register (TAAnCNT)
The value of the 16-bit counter can be read by reading the TAAnCNT register.
(h) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1)
These registers function as capture registers or compare registers depending on the setting of the
TAAnOPT0.TAAnCCSm bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIAAnm pin is detected.
When the registers function as compare registers and when D
m is set to the TAAnCCRm register, the
INTTAAnCCm signal is generated when the counter reaches (Dm + 1), and the output signal of the
TOAAnm pin is inverted.
Remark n = 0 to 3, 5
m = 0, 1