Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)

R01UH0042EJ0500 Rev.5.00 Page 288 of 1513

Aug 12, 2011

When the TAAnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIAAnm pin is

detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, and a capture interrupt request signal

(INTTAAnCCm) is generated.

The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it

generates an overflow interrupt request signal (INTTAAnOV) at the next clock, is cleared to 0000H, and continues counting.

At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR

instruction by software.

Figure 7-35. Basic Timing in Free-Running Timer Mode (Capture Function)

FFFFH

16-bit counter

0000H

TAAnCE bit

TIAAn0 pin input

TAAnCCR0 register

INTTAAnCC0 signal

TIAAn1 pin input

TAAnCCR1 register

INTTAAnCC1 signal

INTTAAnOV signal

TAAnOVF bit

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

Remark n = 0 to 3, 5