Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)

R01UH0042EJ0500 Rev.5.00 Page 287 of 1513

Aug 12, 2011

When the TAAnCE bit is set to 1, 16-bit timer/event counter AA starts counting, and the output signals of the TOAAn0

and TOAAn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TAAnCCRm

is inverted.

The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it

generates an overflow interrupt request signal (INTTAAnOV) at the next clock, is cleared to 0000H, and continues counting.

At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR

instruction by software.

The TAAnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at

that time, and compared with the count value.

Figure 7-34. Basic Timing in Free-Running Timer Mode (Compare Function)

FFFFH

16-bit counter

0000H

TAAnCE bit

TAAnCCR0 register

INTTAAnCC0 signal

TOAAn0 pin output

TAAnCCR1 register

INTTAAnCC1 signal

TOAAn1 pin output

INTTAAnOV signal

TAAnOVF bit

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

Remark n = 0 to 3, 5

m = 0, 1