Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 286 of 1513
Aug 12, 2011
7.5.6 Free-running timer mode (TAAnMD2 to TAAnMD0 bits = 101)
In the free-running timer mode, 16-bit timer/event counter AA starts counting when the TAAnCTL0.TAAnCE bit is set to
1. At this time, the TAAnCCRm register can be used as a compare register or a capture register, depending on the setting
of the TAAnOPT0.TAAnCCS0 and TAAnOPT0.TAAnCCS1 bits.
Figure 7-33. Configuration in Free-Running Timer Mode
TAAnCCR0 register
(capture)
TAAnCE bit
TAAnCCR1 register
(capture)
16-bit counter
TAAnCCR1 register
(compare)
TAAnCCR0 register
(compare)
Output
controller
TAAnCCS0, TAAnCCS1 bits
(capture/compare selection)
TOAAn0 pin output
Output
controller
TOAAn1 pin output
Edge
detector
Count
clock
selection
Edge
detector
Edge
detector
TIAAn0 pin
(external event
count input/
capture
trigger input)
TIAAn1 pin
(capture
trigger input)
Internal count clock
0
1
0
1
INTTAAnOV signal
INTTAAnCC1 signal
INTTAAnCC0 signal
Remark n = 0 to 3, 5
m = 0, 1