Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 282 of 1513
Aug 12, 2011
Figure 7-32. Software Processing Flow in PWM Output Mode (2/2)
TAAnCE bit = 1
Setting of TAAnCCR0 register
Register initial setting
TAAnCTL0 register
(TAAnCKS0 to TAAnCKS2 bits),
TAAnCTL1 register,
TAAnIOC0 register,
TAAnIOC2 register,
TAAnCCR0 register,
TAAnCCR1 register
Initial setting of these
registers is performed
before setting the
TAAnCE bit to 1.
The TAAnCKS0 to
TAAnCKS2 bits can be
set at the same time
when counting is enabled
(TAAnCE bit = 1).
TAAnCCR1 write
processing is necessary
even if only the set cycle
is changed.
When the counter is
cleared after setting,
the values of the
TAAnCCRm register are
transferred to the CCRm
buffer register in a batch.
START
Setting of TAAnCCR1 register
<1> Count operation start flow
<2> TAAnCCR0, TAAnCCR1 register
setting change flow
Setting of TAAnCCR0 register
When the counter is
cleared after setting,
the values of compare
register m are transferred
to the CCRm buffer register
in a batch.
Setting of TAAnCCR1 register
<4> TAAnCCR0, TAAnCCR1 register
setting change flow
Only writing of the TAAnCCR1
register must be performed
when only the set duty factor is
changed. When the counter is
cleared after setting, the
value of compare register m
is transferred to the CCRm
buffer register.
Setting of TAAnCCR1 register
<3> TAAnCCR0, TAAnCCR1 register
setting change flow
TAAnCE bit = 0
Counting is stopped.
STOP
<5> Count operation stop flow
Remark n = 0 to 3, 5
m = 0, 1