Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 278 of 1513
Aug 12, 2011
Figure 7-30. Basic Timing in PWM Output Mode
FFFFH
16-bit counter
0000H
TAAnCE bit
TAAnCCR0 register
CCR0 buffer register
INTTAAnCC0 signal
TOAAn0 pin output
TAAnCCR1 register
CCR1 buffer register
INTTAAnCC1 signal
TOAAn1 pin output
D
10
D
00
D
00
D
01
D
00
D
10
D
11
D
10
D
11
D
01
D
10
D
10
D
00
D
00
D
11
D
11
D
01
D
01
Active period
(D
10
)
Cycle
(D
00
+ 1)
Inactive period
(D
00
− D
10
+ 1)
When the TAAnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
PWM waveform from the TOAAn1 pin.
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TAAnCCR1 register) × Count clock cycle
Cycle = (Set value of TAAnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TAAnCCR1 register)/(Set value of TAAnCCR0 register + 1)
The PWM waveform can be changed by rewriting the TAAnCCRm register while the counter is operating. The newly
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the
16-bit counter is cleared to 0000H.
The compare match interrupt request signal INTTAAnCC0 is generated the next time the 16-bit counter counts after its
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal INTTAAnCC1 is generated when the count value of the 16-bit counter matches the value of
the CCR1 buffer register.
The value set to the TAAnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H.
Remark n = 0 to 3, 5
m = 0, 1