Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 277 of 1513
Aug 12, 2011
7.5.5 PWM output mode (TAAnMD2 to TAAnMD0 bits = 100)
In the PWM output mode, a PWM waveform is output from the TOAAn1 pin when the TAAnCTL0.TAAnCE bit is set to 1.
In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOAAn0 pin.
Figure 7-29. Configuration in PWM Output Mode
CCR0 buffer register
TAAnCCR0 register
16-bit counter
TAAnCCR1 register
CCR1 buffer register
Clear
Match signal
Match signal
INTTAAnCC0 signal
Output
controller
(RS-FF)
Output
controller
TOAAn1 pin
INTTAAnCC1 signal
TOAAn0 pin
TAAnCE bit
Count
clock
selection
Transfer
Transfer
S
R
Remark n = 0 to 3, 5