Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 276 of 1513
Aug 12, 2011
(b) Generation timing of compare match interrupt request signal (INTTAAnCC1)
The generation timing of the INTTAAnCC1 signal in the one-shot pulse output mode is different from other
INTTAAnCC1 signals; the INTTAAnCC1 signal in the one-shot pulse output mode is generated when the count
value of the 16-bit counter matches the value of the TAAnCCR1 register.
Count clock
16-bit counter
TAAnCCR1 register
TOAAn1 pin output
INTTAAnCC1 signal
D1
D1 − 2D1 − 1D1 D1 + 1 D1 + 2
Remark n = 0 to 3, 5
Usually, the INTTAAnCC1 signal is generated the next time the 16-bit counter counts after its count value
matches the value of the TAAnCCR1 register.
In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is
changed to match the change timing of the TOAAn1 pin.