Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 275 of 1513
Aug 12, 2011
(2) Operation timing in one-shot pulse output mode
(a) Note on rewriting TAAnCCRm register
To change the set value of the TAAnCCRm register to a smaller value, stop counting once, and then change
the set value.
If the value of the TAAnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
16-bit counter
0000H
TAAnCE bit
TAAnCCR0 register
INTTAAnCC0 signal
TAAnCCR1 register
INTTAAnCC1 signal
TOAAn1 pin output
External trigger input
(TIAAn0 pin input)
TOAAn0 pin output
(only when software
trigger is used)
D 10 D 11
D 00 D 01
D 00
D 10 D 10 D 10 D 01
D 11
D 00 D 00
Delay
(D
10 )
Delay
(D 10 )
Active level width
(D
00 − D 10 + 1)
Active level width
(D
00 − D 10 + 1)
Delay
(10000H + D
11 )
Active level width
(D
01 − D 11 + 1)
When the TAAnCCR0 register is rewritten from D
00 to D01 and the TAAnCCR1 register from D10 to D11 where
D
00 > D01 and D10 > D11, if the TAAnCCR1 register is rewritten when the count value of the 16-bit counter is
greater than D
11 and less than D10 and if the TAAnCCR0 register is rewritten when the count value is greater
than D
01 and less than D00, each set value is reflected as soon as the register has been rewritten and
compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H.
When the count value matches D
11, the counter generates the INTTAAnCC1 signal and asserts the TOAAn1
pin. When the count value matches D
01, the counter generates the INTTAAnCC0 signal, deasserts the
TOAAn1 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the one-
shot pulse that is originally expected.
Remark n = 0 to 3, 5
m = 0, 1