Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 274 of 1513
Aug 12, 2011
(1) Operation flow in one-shot pulse output mode
Figure 7-28. Software Processing Flow in One-Shot Pulse Output Mode
FFFFH
16-bit counter
0000H
TAAnCE bit
TAAnCCR0 register
INTTAAnCC0 signal
TAAnCCR1 register
INTTAAnCC1 signal
TOAAn1 pin output
External trigger input
(TIAAn0 pin input)
<1> <3>
TAAnCE bit = 1
Register initial setting
TAAnCTL0 register
(TAAnCKS0 to TAAnCKS2 bits),
TAAnCTL1 register,
TAAnIOC0 register,
TAAnIOC2 register,
TAAnCCR0 register,
TAAnCCR1 register
Initial setting of these
registers is performed
before setting the
TAAnCE bit to 1.
The TAAnCKS0 to
TAAnCKS2 bits can be
set at the same time
when counting has been
started (TAAnCE bit = 1).
Trigger wait status
START
<1> Count operation start flow
TAAnCE bit = 0
Count operation is
stopped
STOP
<3> Count operation stop flow
D 10
D 00
D 11
D 01
D 00
D 10
D 11
<2>
D 01
Setting of TAAnCCR0,
TAAnCCR1 registers
As rewriting the
TAAnCCRm register
immediately forwards
to the CCRm buffer
register, rewriting
immediately after
the generation of the
INTTAAnCCR0 signal
is recommended.
<2> TAAnCCR0, TAAnCCR1 register setting change flow
Remark n = 0 to 3, 5
m = 0, 1