Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 273 of 1513
Aug 12, 2011
Figure 7-27. Register Setting for Operation in One-Shot Pulse Output Mode (2/2)
(d) TAAn I/O control register 2 (TAAnIOC2)
00000
TAAnIOC2
Select valid edge of
external trigger input
0 0/1 0/1
TAAnETS1 TAAnETS0
TAAnEES1 TAAnEES0
(e) TAAn counter read buffer register (TAAnCNT)
The value of the 16-bit counter can be read by reading the TAAnCNT register.
(f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1)
If D
0 is set to the TAAnCCR0 register and D1 to the TAAnCCR1 register, the active level width and output
delay period of the one-shot pulse are as follows.
Active level width = (D
0 − D1 + 1) × Count clock cycle
Output delay period = (D1) × Count clock cycle
Caution One-shot pulses are not output even in the one-shot pulse output mode, if the set
value of the TAAnCCR1 register is greater than the set value of the TAAnCCR0 register.
Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are not
used in the one-shot pulse output mode.
2. n = 0 to 3, 5