Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 271 of 1513
Aug 12, 2011
Figure 7-26. Basic Timing in One-Shot Pulse Output Mode
FFFFH
16-bit counter
0000H
TAAnCE bit
TAAnCCR0 register
INTTAAnCC0 signal
TAAnCCR1 register
INTTAAnCC1 signal
TOAAn1 pin output
External trigger input
(TIAAn0 pin input)
TOAAn0 pin output
(only when software
trigger is used)
D 1
D 0
D 0
D 1 D 1 D 1
D 0 D 0
Delay
(D
1 )
Delay
(D 1 )
Delay
(D 1 )
Active
level width
(D
0 − D 1 + 1)
Active
level width
(D
0 − D 1 + 1)
Active
level width
(D
0 − D 1 + 1)
When the TAAnCE bit is set to 1, 16-bit timer/event counter AA waits for a trigger. When the trigger is generated, the
16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOAAn1 pin. After
the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is
generated again while the one-shot pulse is being output, it is ignored.
The output delay period and active level width of the one-shot pulse can be calculated as follows.
Output delay period = (Set value of TAAnCCR1 register) × Count clock cycle
Active level width = (Set value of TAAnCCR0 register − Set value of TAAnCCR1 register + 1) × Count clock cycle
The compare match interrupt request signal INTTAAnCC0 is generated when the 16-bit counter counts after its count
value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTAAnCC1 is
generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register.
The valid edge of an external trigger input or setting the software trigger (TAAnCTL1.TAAnEST bit) to 1 is used as the
trigger.
Remark n = 0 to 3, 5