Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 261 of 1513
Aug 12, 2011
Figure 7-23. Setting of Registers in External Trigger Pulse Output Mode (2/2)
(d) TAAn I/O control register 2 (TAAnIOC2)
00000
TAAnIOC2
Select valid edge of
external trigger input
0 0/1 0/1
TAAnETS1 TAAnETS0TAAnEES1 TAAnEES0
(e) TAAn counter read buffer register (TAAnCNT)
The value of the 16-bit counter can be read by reading the TAAnCNT register.
(f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1)
If D
0 is set to the TAAnCCR0 register and D1 to the TAAnCCR1 register, the cycle and active level of
the PWM waveform are as follows.
Cycle = (D
0 + 1) × Count clock cycle
Active level width = D
1 × Count clock cycle
Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are
not used in the external trigger pulse output mode.
2. n = 0 to 3, 5