Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
R01UH0042EJ0500 Rev.5.00 Page 260 of 1513
Aug 12, 2011
Figure 7-23. Setting of Registers in External Trigger Pulse Output Mode (1/2)
(a) TAAn control register 0 (TAAnCTL0)
0/1 0 0 0 0
TAAnCTL0
Select count clock
0: Stops counting
1: Enables counting
0/1 0/1 0/1
TAAnCKS2 TAAnCKS1 TAAnCKS0 TAAnCE
(b) TAAn control register 1 (TAAnCTL1)
0 0/1 0 0 0
TAAnCTL1
Generates software trigger
when 1 is written
010
TAAnMD2 TAAnMD1 TAAnMD0TAAnEST TAAnEEE
0, 1, 0:
External trigger pulse
output mode
(c) TAAn I/O control register 0 (TAAnIOC0)
0 0 0 0 0/1
TAAnIOC0
0: Disables TOAAn0 pin output
1: Enables TOAAn0 pin output
Sets output level while operation
of TOAAn0 pin is disabled
0: Low level
1: High level
0: Disables TOAAn1 pin output
1: Enables TOAAn1 pin output
Specifies active level of
TOAAn1 pin output
0: Active-high
1: Active-low
0/1 0/1
Note
0/1
Note
TAAnOE1 TAAnOL0 TAAnOE0TAAnOL1
TOAAn1 pin output
16-bit counter
• When TAAnOL1 bit = 0
TOAAn1 pin output
16-bit counter
• When TAAnOL1 bit = 1
Note Clear this bit to 0 when the TOAAn0 pin is not used in the external trigger pulse output
mode.